Job Description - Senior IC Layout Designer IV in San Jose
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Senior IC Layout Designer IV

Ref: US_EN_6_971575_1465731

Posted on 16 September 2022

Senior layout designer will be responsible for the layout of high performance analog cores such as amplifiers, buffers, comparators, regulators, analog-to-digital and digital-to-analog converters, PLL, etc. Responsibilities include working with circuit design engineers to physically layout circuit blocks using foundry CMOS process nodes in 22nm and 40nm following best practices from the industry.

Job requirements include the following qualifications.

  • Thorough knowledge of industry standard EDA tools from Cadence
  • Experience with Mentor and Synopsys desirable
  • Experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc.
  • Experience with floor planning, block level routing and top level chip routing
  • Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration
  • Demonstrated experience with analog layout for silicon chips in mass production
  • Experience with deep sub-micron design in foundry CMOS nodes. Experience with 40nm and 22nm required
  • Experience working with distributed design teams a plus
  • Must possess strong written and verbal communication skills
  • 10+ years of experience in high performance analog layout in advanced CMOS process
  • No preference on industry
  • Equal Opportunity Employer/Veterans/Disabled

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