Vacature Digital IC Verification Engineer (UVM) in Nijmegen | Modis
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Digital IC Verification Engineer (UVM)

Ref: 14913949

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One of the mega trends is the evolution towards self-driving cars. Product Line In-Vehicle Networking is enabling this by bringing ultra-reliable, high-speed, CAN, LIN, Flexray and Ethernet-based data communication into the cars.

We are looking for a: Verification Engineer

Your Responsibilities

  • Verification Engineer (UVM) for Mixed Signal IP development; specify, execute and report Verification simulations of IP to proof the functional, structural and performance compliance before IC Mask Ordering.
  • Define and apply verification test-cases, debug simulations, provide coverage reporting.
  • Collaborate with other teams part of Product development (i.e. system, architecture, industrial engineering, application)


Do you like to work in a highly motivated team, devoted to bring best-in-class next generation In-Vehicle Networking products, in a demanding market with extreme high standards for quality? Are you a trouble shooter, have a hands-on mentality and are eager to find any issue in a new design before it gets at our customers? Then we are looking for you!

Our client provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise. These innovations are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. A global semiconductor company with operations in more than 35 countries, over 45.000 employees and a revenue of over $10 billion.

Automotive is one of the core markets for our client. Thier high performance mixed signal technologies for Automotive applications create new ways to make cars cleaner, safer, more comfortable, and more fun.


Your Profile

  • Bachelor or Master's Degree in electronics or information engineering, with more than 3 years’ experience in IC verification
  • Broad experience and knowledge of verification methodologies and tooling, including SystemVerilog, UVM, constraint random verification and assertions.
  • Hands-on experience with RTL design languages (VHDL/Verilog), scripting languages like Python, TCL and Perl, V-diagram, tools for requirements management (DOORS)
  • Knowledge of CAN and/or Ethernet protocol
  • Experience with lab test infrastructure, emulation and/or prototyping (FPGA and/or virtual prototyping) is a strong benefit.
  • Experience with Analog Mixed signal design, tooling for AMS verification and modelling is a big pre.

Please contact for more information.

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